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1 ? fn6564.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. isl97635a smbus 6-channel led driver the isl97635a is a digitally controlled led driver that controls 6 channels of led current for lcd backlight applications. the isl97635a is capable of driving typically 54 (6x9) pieces of 3.5v/30ma or 60 (6x10) pieces of 3.2v/20ma leds. the isl97635a contains 6 channels of voltage controlled cu rrent sources with typical currents matching of 1%, which compensate for the non-uniformity effect of forward voltages variance in the led stacks. to minimize the voltage headroom and power loss in the typical multi-strings operation, the isl97635a features a dynamic headroom control that monitors the highest led forward voltage string and uses its feedback signal for output regulation. the led dimming control can be achieved through a smbus, an external pwm, or a variable dc (analog light sensor) input. smbus controlled dimming allows 256 levels each of pwm and dc current adjustments. the smbus pwm dimming frequency can be adjusted from 100hz to 5khz by an external capacitor. external pwm input allows up to 20khz audio noise free pwm dimming. the smbus pwm setting and an external pwmi signal can also be combined to provide a dynamic pwm dimming that complies with intel?s dpst (display power saving technology) requirement. one or more channels can be selected sequentially in any order allowing scrolling in rgb led backlighting applications. the isl97635a features extens ive protection f unctions that include string open and short circuit detections, ovp, otp, thermal shutdown and an optional input overcurrent protection with master faul t disconnect switch. the fault conditions will be recorded in the fault/status register. there are selectable short-circuit thresholds and the switching frequency can be programmed between 600khz and 1.2mhz. available in the 24 ld 4mmx4mm qfn, the isl97635a operates from -40c to +85 c with input voltage ranging from 6v to 24v for high leds count applications. features ? 6 channels ? 6v to 24v input ? 34.5v output max ? drive maximally 54 (3.5v/30ma each) or 60 (3.2v/20ma each) leds ? current matching 1% typ ? dynamic headroom control ? dimming controls - smbus 8-bit pwm current control - smbus 8-bit dc current control - external pwm input up to 20khz dimming - smbus and external pwm dpst dimming control - dc-to-pwm dimming control ? protections - string open circuit detection - string short circuit detection with selectable thresholds - over-temperat ure protection - overvoltage protection - input overcurrent protection with disconnect switch ? 600khz/1.2mhz selectable f sw ? selectable channels allows scrolling backlight ? 24 ld (4mmx4mm) qfn package ? pb-free (rohs compliant) applications ? notebook displays wled or rgb led backlighting ? lcd monitor led backlighting ? automotive displays led backlighting ? automotive or traffic lighting ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL97635AIRZ* 976 35airz 24 ld 4x4 qfn l24.4x4d *add ?-t? or ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet december 22, 2008
2 fn6564.2 december 22, 2008 typical application circuit smbdat vbl+ = 6v to 24v pwmi/en pwmo comp vin fault ovp pgnd rset v out = 34.5v, 30ma per string vdc lx smbclk iin0 iin3 iin2 iin4 iin5 fpwm 23 24 1 2 6 4 11 3 9 10 12 17 13 14 15 16 19 21 22 lx 20 pgnd 18 gnd 5 isl97635a iin1 isl97635a
3 fn6564.2 december 22, 2008 block diagram figure 1. isl97635a block diagram 34.5v, 30ma per string (6 x 9 = 54 white leds) generator vin comp + - + - iin0 iin5 vbl+ = 6v to 24v fet driver reg lx isl97635a ramp comp imax ilimit interface pwm/oc/sc pwm brightness control device control fault/status identification registers highest vf string detect dc brightness control vdc sensor f pwm led pwm control pgnd configuration fault + - gnd reference smbclk smbdat vin gm amp + - + - pwmo logic ovp lx osc and = 0 am oc, sc detect fault/status register fault/status register temp fault/status register pwmi rset + - oc, sc detect smbus interface isl97635a
4 fn6564.2 december 22, 2008 absolute maxi mum ratings (t a = +25c) thermal information vin, fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 24v vdc, comp, rset . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v smbclk, smbdat, fpwm, pwmo, en/pwm . . . . . -0.3v to 6.5v ovp, iin0 - iin5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 36v pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to gnd pin operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . 39 2 thermal characterization (typical, note 3) psi jt (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~0.7 maximum continuous junction temperature . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside assumed under ideal case temperature . 3. psi jt is the junction-to-top thermal resistance. if the package top te mperature can be measured, with this rating then the die junct ion temperature can be estimated more accurately than the jc and jc thermal resistance ratings. 4. limits established by characteri zation and are not production tested. electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k , unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. parameter description condition min typ max unit general vin backlight supply voltage 9 leds per channel (3.5v/30ma type) 6 24 v ivin_stby vin shutdown current 5a v out output voltage 34.5 v v uvlo undervoltage lockout threshold 2.45 2.8 v v uvlo_hys undervoltage lockout hysteresis 300 mv regulator v dc ldo output voltage vin >6v 5.0 5.5 v i vdc_stby standby current en/pwm = 0v 20 a i vdc active current en/pwm = 5v 10 ma v ldo vdc ldo dropout voltage vin > 5.5v, 30ma 30 200 mv ss soft-start 1ms enmin minimum enable signal 40 s boost swilimit boost fet current limit t a = +25c 2.3 3.2 a t a = -40c to +85c 2.2 a r ds(on) internal boost switch on-resistance 130 260 m isl97635a
5 fn6564.2 december 22, 2008 eff_peak peak efficiency v in = 18v, 54 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 91 % v in = 12v, 54 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 88 % v in = 6v, 54 leds, 20ma each, l = 8.2h with dcr 106m , t a = +25c 86 % i out / v in line regulation 0.1 % d max boost maximum duty cycle 82 % d min boost minimum duty cycle 7% f osc_hi lx frequency register 0x08, f sw = 1 1.0 1.2 1.3 mhz f osc_lo lx frequency register 0x08, f sw = 0 550 600 650 khz ilx_leakage lx leakage current vlx = 36v, en = 0 10 a reference i match channel-to-channel current matching i out = 30ma, brt = 255 -3.5 1 +3.5 % i acc current accuracy 3 % fault detection v sc short circuit threshold reg0x08 = 0x0f or 0x0b reg0x00 = 0xff 7.8 8 8.8 v reg0x08 = 0x0e or 0x0a reg0x00 = 0xff 2.8 3.1 3.8 v v temp_acc over-temperature threshold accuracy 5 c v ovplo overvoltage limit on ovp pin 1.17 1.2 1.23 v ovp hys ovp hysteresis 20 mv ovp fault ovp short detection fault level 300 mv smbus interface vil guaranteed range for data, clock input low voltage 0.8 v vih guaranteed range for data, clock input high voltage 2.1 vdd v vol smbus data line logic low voltage with 1.1k series resistor from data bus to smbdat pin i pullup = 350a 0.4 v smbus data line logic low voltage without series resistor from data bus to smbdat pin i pullup = 4ma 0.17 v i leak input leakage on smbdata/smbclk -1 1 a v dd nominal bus voltage 3v to 5v 10% 2.7 5.5 v smbus timing specifications (note 4) f smb smbus clock frequency 10 100 khz t buf bus free time between stop and start condition 4.7 s t hd:sta hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 s t su:sta repeated start condition setup time 4.7 s t su:sto stop condition setup time 4.0 s t hd:dat data hold time 300 ns electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k , unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description condition min typ max unit isl97635a
6 fn6564.2 december 22, 2008 t su:dat data setup time 250 ns t low clock low period 4.7 s t high clock high period 4.0 50 s t f clock/data fall time 300 ns t r clock/data rise time 1000 ns general timing specifications (note 4) t 1 minimum setup time between v in rising above vuvlo with en = 1 and smbus communications en = 1, t a = +25c, vdc capacitor < 10f 80 s t 2 minimum setup time between en going high with v in above vuvlo and smbus communications v in > vuvlo, t a = +25c, vdc capacitor < 10f 80 s t 3 minimum time between v in rising above vuvlo with en = 1 to smbus bl ctrl on en = 1, t a = +25c 4.5 ms t 4 minimum time between en going high with v in above vuvlo to smbus bl ctrl on v in > vuvlo, t a = +25c 4.5 ms t 5 minimum time for led output to respond to smbus data at any levels v in > vuvlo, en = 1, t a = +25c 5 s t 6 response time between backlight ctrl off with boost not switching to backlight ctrl on with boost switching v in > vuvlo, en = 1, t a = +25c 5 s t 7 response time between backlight ctrl on with boost switching to backlight ctrl off with boost not switching v in > vuvlo, en = 1, t a = +25c 5 s t 8 led channel short circuit fault detection to status register data ready v in > vuvlo, en = 1, t a = +25c, leds active 6ms t 9 v out-gnd short circuit detection during operation to status register data ready v in > vuvlo, en = 1, t a = +25c, fault fet used 5s t 10 time between vin rising above vuvlo with en = 1 and v out-gnd short being reported in status register en = 1, vdc capacitor < 10f, t a = +25c, fault fet used. 30 ms t 11 time between en going high with v in above vuvlo and a v out-gnd short being reported in status register v in > vuvlo, vdc capacitor < 10f, t a = +25c, fault fet used. 30 ms current sources v headroom dominant channel current source headroom at iin pin i led = 20ma, t a = +25c 100 mv v rset voltage at rset pin r set = 36.6k 680 700 720 mv i ledmax maximum led current per channel r set = 20.9k 35 ma pwm generator (note 4) fpwm generated pwm frequency c fpwm = 27nf, c pwmo = 220nf 200 hz dpwm duty cycle of generated pwm (dc-to-pwm) v pwmo = 0.3v cfpwm = 27nf 90 % v pwmo = 1.1v cfpwm = 27nf 10 % t max_pwm_off maximum pwmi off-time before shutdown en/pwmi toggles 28 ms electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k , unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description condition min typ max unit isl97635a
7 fn6564.2 december 22, 2008 fault pin i fault fault pull-down current v in = 12v 10 18 30 a v fault fault clamp voltage with respect to vin v in = 12, v in - v fault 7.5 v ilxstart-up lx start-up current vdc = 5.2v 1 2.7 7 ma electrical specifications all specifications below are tested at t a = -40c to +85c; v in = 12v, en = 5v, r set = 36.6k , unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description condition min typ max unit typical performance curves figure 2. efficiency, l = 8.2h with dcr = 106m , c o = 4x4.7f/50v figure 3. efficiency, l = 10h with dcr = 129m , c o = 4x4.7f/50v figure 4. 3 efficiency, l = 10h with dcr = 500m , 1mm, c o = 4x4.7f/50v figure 5. current regulation 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 i o (ma) efficiency (%) l = 8.2h ihlp-2525bd-01 dcr = 106m i sat = 3a 7s6p - 18v 9s6p - 6v 7s6p - 6v 9s6p - 12v 7s6p - 12v 9s6p - 18v 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 i o (ma) efficiency (%) l = 10h ihlp-2525bd-01 dcr = 129m i sat = 2.5a 7s6p - 6v 7s6p - 12v 7s6p - 18v 9s6p - 6v 9s6p - 12v 9s6p - 18v 66 68 70 72 74 76 78 80 82 84 86 88 90 92 0 20 40 60 80 100 120 140 i o (ma) efficiency (%) l = 10h dcr ~ 500m <1mm height 9s6p - 6v 7s6p - 6v 9s6p - 12v 9s6p - 18v 7s6p - 12v 7s6p - 18v -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 4 6 8 101214161820222426 v in (v) current variation (%) 20ma isl97635a
8 fn6564.2 december 22, 2008 figure 6. channel-to-channel current matching figure 7. current matching vs duty cycle vs dimming frequency figure 8. pwm dimming linearity figure 9. lx, iin, il and lo figure 10. il at 50% pwm dimming figure 11. i l zoom in at pwm dimming zoom in typical performance curves (continued) -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 channels current matching 6p9s = 54 leds 6v/1ma 6v/20ma 12v/1ma 12v/20ma 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 pwm duty cycle current matching (%) 10khz 200hz 1khz 100hz 20khz v in = 12v 0 20 40 60 80 100 120 140 160 180 0 102030405060708090100 pwm duty cycle (%) total output current (ma) v in = 18v v in = 6v v in = 12v 6 channels 9 leds per channel isl97635a
9 fn6564.2 december 22, 2008 figure 12. i led at 50% pwm dimming figure 13. lx at 50% pwm dimming figure 14. lx zoom in at 50% dimming figure 15. ripple voltage figure 16. ripple voltage zoom in typical performance curves (continued) isl97635a
10 fn6564.2 december 22, 2008 pinout isl97635a (24 ld qfn) top view vdc vin comp fault lx lx nc nc iin5 iin4 rset iin3 smbclk smbdat fpwm pwmo gnd pwmi/en pgnd pgnd ovp iin0 iin1 iin2 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 pin descriptions (i = input, o = output, s = supply) pin name type description 1 smbclk i smbus serial clock input 2 smbdat i/o smbus serial data input and output 3 fpwm i connect a capacitor between fpwm and gnd to set the dpwm frequency. fpwm = 5.4/c fpwm if smbus pwm or dpst mode is used, connect c fpwm to gnd to set the dimming frequency. also, connect c pwmo between v pwmo and gnd pins for dpst operation. if dc-to-pwm mode is used, connect c fpwm to set the dimming frequency and apply a 0.21v to 1.21v at v pwmo . 4 pwmo i/o pwmi buffered output. if one connects a capacitor between pwmo and gnd, it forms a lowpass filter with an internal 40k resistor to filter the pwmi signal for dpst operation when reg 0x01 = 0x01. if one applies a 0.2v to 1.2v dc input voltage, the output will be pwm with duty cycle proportional to the dc input. 5 gnd s analog gnd and led power return 6 pwmi/en i dual functions: enable pin and pwm brightnes s control pin or dpst control input. do not let pwmi/en floating. the device needs 4ms for initial power-up enable, then this pin can be applied with a pwm signal with off time no longer than 28ms. 7, 8 nc - no connect. can be floating or grounded 9 iin5 i input 5 to current source, fb, and monitoring 10 iin4 i input 4 to current source, fb, and monitoring 11 rset i resistor connection for setting led curren t, (see equation 1 for calculating the iledmax) 12 iin3 i input 3 to current source, fb, and monitoring 13 iin2 i input 2 to current source, fb, and monitoring 14 iin1 i input 1 to current source, fb, and monitoring 15 iin0 i input 0 to current source, fb, and monitoring 16 ovp i overvoltage protection input 17, 18 pgnd s power ground (lx power return) 19, 20 lx i input to boost switch 21 fault o fault disconnect switch 22 comp o boost compensation pin 23 vin s input voltage for the device and led power 24 vdc s de-couple capacitor for internally generated supply rail. if 2.7v < vbl+ < 5.5v, apply vdc directly with a supply voltage of 2.7v to 5.5v isl97635a
11 fn6564.2 december 22, 2008 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97635a employes current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight applications where the power can be a series of drained batteries or instantly changed to an ac/dc adapter without rendering a noticeable visual nuisance. the number of leds that can be driven by isl97635a depends on the type of led chosen in the application. the isl97635a is capable of boosting up to 34.5v and typically driving 9 leds in series for each of the 6 channels, enabling a total of 54 pieces of the 3.5v/30ma type of leds. enable and pwmi the en/pwmi pin serves dual purposes; it is used as an enable signal and can be used for pwm input signal for dimming. if a pwm signal is applied to this pin, the first pulse of minimum 40s will be used as an enable signal. if there is no signal for longer than 28ms, the device will enter shutdown. the en/pwmi pin cannot be floating, thus, a 10k pull-down resistor may need to be added. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 17. the led peak current is set by translating the r set current to the output with a scaling factor of 733/r set . the source terminals of the current source mosfets are designed as 100mv to minimize the power lo ss. the sources of errors of the channel-to-channel current matching come from the op amp?s offset, internal layout, reference, and current source resistors. these parame ters are optimized for current matching and absolute current accuracy. on the other hand, the absolute accuracy is additionally determined by the external r set , and therefore, additional tolerance will be contributed by the current setting resistor. a 1% tolerance resistor is therefore recommended. dynamic headroom control the isl97635a features a proprietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest volt age from any of the iin pins. when this lowest i in voltage is lower than the short circuit threshold, v sc , such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level such that the lo west iin pin is at the target headroom voltage. since all led stacks are connected to the same output voltage, the other iin pins will have a higher voltage, but the regulated cu rrent source circuit on each channel will ensure that each channel has the same programmed current. the outpu t voltage will regulate cycle by cycle and it is always re ferenced to the highest forward voltage string in the architecture. dimming controls the isl97635a allows two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment. 2. pwm chopping of the led current defined in step 1. there are various ways to achieve dc or pwm current control, which will be described in the following. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current, as shown in equation 1: dc current adjustment once r set is fixed, the led dc current can be adjusted through register 0x07 (brtdc), as shown in equation 2: figure 17. simplified current source circuit ref + - + - pwm dimming rset + dc dimming ref + - + - rset - i ledmax 733 r set --------------- = (eq. 1) i led 2.87 brtdc r set ? = (eq. 2) isl97635a
12 fn6564.2 december 22, 2008 brtdc can be programmed from 0 to 255 in decimal and defaults to 255 (0xff). if left at the default value, led current will be fixed at i ledmax . brtdc can be adjusted dynamically on the fly during operation. brtdc = 0 disconnects all channels and iled is guaranteed to be <10a at this state. for example, if the maximum required led current (i ledmax ) is 20ma, rearranging equation 1 yields equation 3: if brtdc is set to 200, then: pwm control the isl97635a provides four different pwm dimming methods, as described in the following. each of these methods results in pwm chopping of the current in the leds for all 6 channels to provide an average led current. during the on-periods, the led current will be defined by the value of r set and brtdc, as described in equations 1 and 2. the source of the pwm signal can be described as follows: 1. internally generated 256 step duty cycle programmed through the smbus. 2. external signal from pwmi. 3. dpst mode. internally generated signal with a duty cycle defined by the product of the external pwmi and smbus programmed pwm at the internal setting frequency. 4. dc-to-pwm control. the default pwm dimming is in dpst mode. in all four methods, the average led current of each channel is controlled by i led and the pwm duty cycle in percent as shown in equation 5: method 1 (internal mode , smbus controlled pwm) the average led current of each channel is controlled by the internally generated pwm signal as shown in equation 6: where brt is the pwm brightness level programmed in the register 0x00. brt ranges from 0 to 255 in decimal and defaults to 255 (0xff). brt = 0 disconnects all channels and i led is guaranteed to be <10a in this state. to use only the smbus contro lled pwm brightness control, users need to set register 0x01 to 0x05 with en/pwmi in logic high. the smbus controlled pwm frequency is adjusted by a capacitor at the fpwm pin, which will be described in ?pwm dimming frequency adjustment? on page 13. method 2 (external mode) the average led current of each channel can also be controlled by an external pwmi signal, as shown in equation 7: the pwm dimming frequency can be for example 20khz but there are a minimum on and off time requirements such that the dimming will be in the range of 10% to 99.5%. if the dimming frequency is below 5khz, the dimming range can be 1% to 99.5%. the pwm dimming off time cannot be longer than 28ms or else the driver will enter shutdown. to use pwmi only brightness control, users need to set register 0x01 to 0x03. method 3 (dpst mode) the average led current of each channel can also be controlled by the product of the smbus controlled pwm and the external pwmi signals as follows: where: therefore: where brt is the value held in re gister 0x00 (default setting 0xff) controlled by smbus an d pwmi is the duty cycle of the incoming pwmi signal. in this way, the users can change the pwm current in ratiometri c manner to achieve dpst compliance backlight dimming. to use the dpst mode, users need to set register 0x01 to 0x01 with the external pwm signal. the dpst mode pwm frequency is adjusted by a capacitor at the fpwm pin. also, a c pwmo capacitor is also needed, which will be described in ?pwm dimming frequency adjustment? on page 13. for example, if the smbus controlled pwm duty is 80% dimming at 200hz (see c fpwm in equation 10) and the external pwmi duty cycle is 60% dimming at 1khz, the resultant pwm duty cycle is 48% dimming at 200hz. method 4 (analog mo de, dc-to-pwm mode) by overdriving the pwmo pin with a dc voltage between 0.21v and 1.21v, the average led current of each channel r set 733 0.02 ? 36.6k == (eq. 3) i led 2.87 ? 200 36600 ? 15.7ma == (eq. 4) i led ave () i led pwm = (eq. 5) i led ave () i led brt 255 ? () = (eq. 6) i led ave () i led pwmi = (eq. 7) i led ave () i led xpwm dpst = (eq. 8) pwm dpst brt 255 ? pwmi = (eq. 9) i led ave () i led brt 255 ? pwmi = (eq. 10) isl97635a
13 fn6564.2 december 22, 2008 is controlled by the internally generated pwm signal as shown in equation 11: where brt is the value held in register 0x00 (default setting 0xff). the pwmo pin is inte rnally driven to 0.21v via a 40k resistor when the pwmi/en pin is in logic high, any overdrive circuit will need to be able to drive up to 40a in order to overcome this. the dc-to-pwm controlled pwm frequency is adjusted by a capacitor at the fpwm pin, which will be described in ?pwm dimming frequency adjustment? on page 13. for example, if pwmo is applied with a dc voltage 1.21v, the output will be zero. on the other hand, if the pwmo is applied with a dc voltage 0.21v, the pwm duty cycle will be at its maximum. if the pwmo pin is applied with a dc voltage of 0.31v, the pwm du ty cycle will be at 90% at 200hz if c fpwm = 27nf. pwm dimming frequency adjustment (applicable to smbus controlled pwm, dpst, and dc-to-pwm modes) except for the external pwm dimming mode where the frequency follows the external signal?s, the dimming frequencies of the other modes are set by an external capacitor c fpwm at the fpwm pin as shown in equation 12: where f pwm is the desirable pwm dimming frequency. for example, if fpwm = 200hz, c fpwm = 5.4/200 = 27nf the pwm dimming frequency can be for example 20khz but there are a minimum on and off ti me requirements such that the dimming will be in the rang e of 10% to 99.5%. if the dimming frequency is below 5khz, the dimming range can be 1% to 99.5%. in the dpst and dc-to-pwm modes, a c pwmo capacitor is also needed. an internal 40k and an external c pwmo at the pwmo pin form a low pass network to filter the pwmi to an averaged dc. as a result, the time constant of the 40k and c pwmo should be significantly larg er than the external pwmi period, t, such that: for example, if f pwm is 200hz and external pwmi is 1khz or above, a 220nf c pwmo can be chosen that allows the external pwmi signal to be filt ered as an averaged dc. also, the f pwm frequency in the dpst mode should be limited between 100hz to 2khz and at least five times smaller than the external pwmi frequency when dpst mode is used. switching frequency an internal clock of 1.2mhz is used for the boost regulator control of the lx pin in default. there are 2 levels of switching frequencies: 600khz or 1.2mhz. each can be programmed in the configurat ion register 0x08 bit 2. the default switching frequency is at 1.2mhz. 5v low dropout regulator a 5.2v ldo regulator is present at the vdc pin to develop the necessary low voltage supply which is used by the chips internal control circuitry. because vdc is an ldo pin, it requires a bypass capacitor of 1f or more for the regulation. for applications with an input voltage 5.5v, the vin and vdc pins can be conn ected together. the vdc pin can be used as a coarse reference with few ma sourcing capability. in-rush control and soft-start the isl97635a has separately built-in independent inrush control and soft-start functions. the inrush control function is built around the short circuit protection fet, and is only available in applications which include this device. at start-up, the fault protection fet is turned on slowly due to a 30a pull-down current output from the fault pin. this discharges the fault fet's gate- source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the weakly turned on fet before it becomes fully enhanced. this results in a low in-rush current. this current can be further reduced by adding a capacitor (in the 1nf to 5nf range) across the gate-source terminals of the fet. once the chip detects that the fault protection fet is turned on hard, it is assumed that inru sh is complete. at this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching terminated in any cycle where the current exceeds the current limit. the isl97635a includes a soft-start feature where this current limit starts at a low value (375ma). this is stepped up to the final 3a current limit in seven furt her steps of 375ma. these steps will happen over a 1ms total time, such that after 1ms the final limit will be reached. this allows the output capacitor to be charged to the required val ue at a low current limit and prevents high input current fo r systems that have only a low to medium output current requirement. for systems with no ma ster fault protection fet, the in-rush current will flow towards c out when vin is applied and it is determined by the ramp rate of vin and the values of c out and l. i led ave () i led brt 255 1 v pwmo () 0.21 ? () ? () ? = (eq. 11) c fpwm 5.4 f pwm ? = (eq. 12) 40k x c pwmo >t (eq. 13) isl97635a
14 fn6564.2 december 22, 2008 fault protection and monitoring the isl97635a features extens ive protection functions to cover all the perceivable failure conditions. the failure mode of a led can be either open circuit or as a short. the behavior of an open circuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. all led faults are reported via the smbus interface to r egister 0x02 (fault/status register). the controller is able to determine which channels have failed via register 0x09 (o utput masking register). the controller can also choose to use register 0x09 to disable faulty channels at start-up, resulting in only further faulty channels being reported by register 0x02. due to the lag in boost response to any load change at its output, certain transient event s (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97635a uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of t he led stacks to fault out. see table 1 for more details. a fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels. the control device logic will remain functional such that the fault/status register can be interrogated by the system. the r oot cause of t he failure will be loaded to the volatile fault/status register so that the host processor can interrogate the data for failure monitoring. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. there are two selectable levels of short circuit threshold (3.1v and 8.0v) that can be programmed through the configuration register 0x08 bi t 0. when an led becomes shorted, the action taken is de scribed in table 1. the default short circuit threshold is 8v. the detection of this failure mode can be disabled via register 0x08 bit 1 if required. open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the isl97635a monitors the current in each channel such that any string which reaches at least 75% of the intended output current is considered ?good?. should the current subsequently fall below 50% of the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the isl97635a reach the ovp limit or should the lower over-temperature threshold be reached, all channels which ar e not ?good? will immediately be considered as ?open circuit?. detection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. this time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. some users employ some special types of leds that have zener diode structure in parallel with the led for esd enhancement and enabling open circuit operation. when this type of led is open circuit ed, the effect is as if the led forward voltage has increased but no lighting. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, allowing all other leds in the string to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. this is due to the increased forward volta ge of the faulty channel making all other channels look as if they have led shorts. see table 1 for details regarding responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit monitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as equation 14: these resistors should be large to minimize the power loss. for example, a 1m r upper and 39k r lower sets ovp to 32.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. undervoltage lockout if the input voltage falls below the uvlo level of 2.45v, the device will stop switching and reset. operation will restart when the voltage comes back into the operating range. input overcurrent protection during normal switching operation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal switch will be turned off. this monitoring happens on a cycle-by-cycle basis in a self protecting way. additionally, the isl97635a monitors the voltage at the lx and ovp pins. at start-up, a fi xed current is injected out of the lx pins and into the output capacitor. the device will not start-up unless the voltage at lx exceeds 1.2v. furthermore, should the voltage at lx not rise above this threshold during any subsequent period where the power fet is not switched on, it will immediately disable the input protection fet. the ovp pin is also monitored such that if it rises above and ovp 1.21v r upper r lower + () r lower ? = (eq. 14) isl97635a
15 fn6564.2 december 22, 2008 subsequently falls below 20% of the target ovp level, the input protection fet will also be switched off. over-temperature protection (otp) the isl97635a includes two over-temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as ?open circuit? and disabled after a time-out period. this time-out period is also reduce d to 800s when it is above the lower threshold. the intention of the lower threshold is to allow bad channels to be isol ated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c. each time this is reached, the boost will stop s witching and the output current sources will be switched off. once the device has cooled to approximately +100c, the dev ice will restart with the dc led current level reduced to 77% of the initial setting. if the dissipation problem persists, su bsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 53% and finally 30%. hitting of the upper threshold will also set the thermal fault bit of the fault/status register 0x02. unless disabled via the en pin, the device stays in an active state throughout, allows the external processor to interrogate the fault condition. for the extensive fault protection conditions, please refer to figure 18 and table 1 for details. figure 18. simplified fault protections q5 vsc iin5 vset dc current pwm/oc0/sc0 ref fet driver lx imax ilimit driver fault ovp vin t2 otp thrm shdn q0 vsc iin0 vout smbus control logic fault/ status register vset pwm/oc5/sc5 temp sensor logic lx t1 otp thrm shdn o/p short + - + - reg vset/2 isl97635a
16 fn6564.2 december 22, 2008 table 1. protections table case failure mode detection mode failed channel action good channels action vout regulated by 1 ch0 short circuit upper over-temperature protection limit (otp) not triggered and viin0 < vsc ch0 on and burns power ch1 through ch5 normal highest vf of ch1 through ch5 2 ch0 short circuit upper otp triggered but vin0 < vsc ch0 goes off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. thermal event reported in fault/status register. same as ch0 highest vf of ch1 through ch5 3 ch0 short circuit upper otp not triggered but viin0 > vsc ch0 doubled after 6ms time-out. time-out reduced to 420s if above lower otp limit ch1 through ch5 normal highest vf of ch1 through ch5 4 ch0 open circuit with infinite resistance upper otp not triggered and viin0 < vsc vout will ramp to ovp. ch0 will time-out after 6ms (800s if above lower otp limit) and switch off. vout will drop to normal level. ch1 through ch5 normal highest vf of ch1 through ch5 5 ch0 led open circuit but has paralleled zener upper otp not triggered and viin0 < vsc ch0 remains on and has highest vf, thus vout increases ch1 through ch5 on, q1 through q5 burn power vf of ch0 6 ch0 led open circuit but has paralleled zener upper otp triggered but viin0 < vsc ch0 goes off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. thermal event reported in fault/status register. same as ch0 vf of ch0 7 ch0 led open circuit but has paralleled zener upper otp not triggered but viin0 > vsc ch0 off ch1 through ch5 normal highest vf of ch1 through ch5 upper otp not triggered but viinx > vsc ch0 remains on and has highest vf, thus vout increases. vout increases then ch-x switches off. this is an unwanted shut off and can be prevented by setting ovp and/or vsc at an appropriate level. vf of ch0 8 channel-to-channel vf too high lower otp triggered but viinx < vsc any channel at below 50% of the target current will fault out after 400s. remaining channels driven with normal current. highest vf of ch0 through ch5 9 channel-to-channel vf too high upper otp triggered but viinx < vsc all channels switched off until chip cooled and then comes back on with current reduced to 76%. further otp triggers result in reduction to 53%, then 30%. thermal event reported in fault/status register. highest vf of ch0 through ch5 10 output led stack voltage too high vout > vovp driven with normal current. any channel that is below 50% of the target current will time-out after 6ms. highest vf of ch0 through ch5 11 vout/lx shorted to gnd lx current and timing are monitored. ovp pin monitored for excursions below 20% of ovp threshold fault switch disabled and system s hutdown until fault goes away, vout is checked at startup with a low curr ent from lx to check for presence of short before the fault switch is enabled. isl97635a
17 fn6564.2 december 22, 2008 figure 19. smbus interface v ih v il v ih v il t r t low t hd:sta t hd:dat t f t high t su:dat t su:sta s s p p t su:sto smbdat smbclk notes: smbus description s = start condition p = stop condition a = acknowledge a = not acknowledge r/w = read enable at high; write enable at low t buf figure 20. write byte protocol master to slave slave to master 171181811 s slave address w a command code a data byte ap figure 21. read byte protocol master to slave slave to master 1711 8 11811811 s slave address w a command code a s slave address r a data byte a p isl97635a
18 fn6564.2 december 22, 2008 write byte the write byte protocol is only three bytes long. the first byte starts with the slave address followed by the ?command code,? which translates to the ?register index? being written. the third byte contains the data byte that must be written into the register selected by the ?command code?. a shaded label is used on cycles during which the slaved backlight controller ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? read byte as shown in the figure 21, the 4 byte long read byte protocol starts out with the slave address followed by the ?command code? which translates to the ?register index.? then the bus direction turns around with the re-broadcast of the slave address with bit 0 indicating a read (?r?) cycle. the fourth byte contains the data being returned by the backlight controller. that byte value in the data byte reflects the value of the register being queried at the ?command code? index. note the bus directions, which are highlighted by the shaded label that is used on cycles duri ng which the slaved ba cklight controller ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? slave device address the slave address contains in 7 msb plus one lsb as r/w bit but these 8 bits are usually called slave address byte. as shown in figure 22, the high nibble of the slave address byte is 0x5 or 0101b to denote the ?backl ight controller class.? bit 3 in the lower nibble of the slave address byte is 1. bit 0 is always the r/w bit, as specified by the smbus protocol. note: in this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. therefor e, if the device is in the write mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. if the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. the backlight controller may sense the state of the pins at por or during normal operation?the pins will not change state while the device is in operation. smbus register definitions the backlight controller registers are byte wide and accessible via the smbus read/wr ite byte protocols. their bit assignments are provided in the following sections with reserved bits containing a default value of ?0?. figure 22. slave address byte definition device identifier device address r e a d / w r i t e b i t msb lsb 0101100r/w table 2a. register listing address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value smbus protocol 0x00 pwm brightness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 0xff read and write 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl 0x00 read and write 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault 0x00 read only 0x03 identification register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 0xc8 read only 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 0xff read and write 0x08 configuration register reserved reserved reserved reserved reserved fsw vsc1 vsc0 0xxf read and write 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 0xff read and write isl97635a
19 fn6564.2 december 22, 2008 pwm brightness control register (0x00) the brightness control resolution has 256 steps of pwm duty cycle adjustment. the bit assignment is shown in figure 23. all of the bits in th is brightness control register can be read or write. step 0 corresponds to the minimum step where the current is less than 10a. step1 to step 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. ? an smbus write byte cycle to register 0x00 sets the pwm brightness level only if the back light controller is in smbus mode (see table 3 operating modes selected by device control register bits 1 and 2). ? an smbus read byte cycle to register 0x00 returns the programmed pwm brightness level regardless of the value of pwm_sel. ? an smbus setting of 0xff for register 0x00 sets the backlight controller to the maximum brightness. ? an smbus setting of 0x00 for register 0x00 sets the backlight controller to the minimum brightness output in which the led current is gua ranteed to be less than 10a. ? default value for register 0x00 is 0xff. table 2b. data bit descriptions address register data bit descriptions 0x00 pwm brightness control register brt[7..0] = 256 steps of dpwm duty cycle brightness control 0x01 device control register pwm_md = pwm mode select bit (1 = absolute brightness, 0 = % change), default = 0 pwm_sel = brightness control select bit (1 = cont rol by pwmi, 0 = control by smbus), default = 0 bl_ctl = bl on/off (1 = on, 0 = off), default = 0 0x02 fault/status register 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bl_stat = bl status (1 = bl on, 0 = bl off) ov_curr = input overcurrent (1 = overcurrent condition, 0 = current ok) thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) fault = fault occurred (logic ?or? of all of the fault conditions) 0x03 identification register mfg[3..0] = manufacturer id (16 vendors available. in tersil is vendor id 9) rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) 0x07 dc brightness control register brtdc[7..0] = 256 steps of dc brightness control 0x08 configuration register vsc[1..0] = short circuit thresholds selection fsw[2] = switching frequencies selection 0x09 output channel mask / fault readout register ch[5..0] = output channel read and write. in write, 1 = channel enabled, 0 = channel disabled. in read, 1 = channel ok, 0 = channel not ok/channel disabled pwm_md pwm_sel mode x 1 pwmi mode 1 0 smbus mode 0 0 smbus and pwmi mode with dpst vsc1 vsc0 operation 0 x no vsc error detection 1 0 vsc = 3.1v 15% 1 1 vsc = 8v 15% fsw operation 0f sw = 600khz 1f sw = 1.2mhz isl97635a
20 fn6564.2 december 22, 2008 device control register (0x01) this register has two bits that control the operating mode of the backlight controller and a single bit that controls the bl on/off state. the remaining bits are reserved. the bit assignment is shown in figure 24. all other bits in the device control register will read as low unless otherwise written. bits 7 and 6 are not implemented and will always read low. the pwm_sel bit determines wh ether the smbus or pwmi input should drive the output brightness in terms of pwm dimming. when pwm_sel bit is 1, the pwmi drives the output brightness regardless of what the pwm_md is. when the pwm_sel bit is 0, the pwm_md bit selects the manner in which the pwm dimming is to be interpreted; when this bit is 1, the pwm dimming is based on the smbus brightness setting. when this bit is 0, the pwm dimming reflects a percentage change in the current brightness programmed in the smbus register 0x00, i.e. dpst (display power saving technology) mode as shown in equation 15: where: cbt = current brightness setting from smbus register 0x00 without influence from the pwmi pwmi = is the percent duty cycle of the pwmi for example, the cbt = 50% duty cycle programmed in the smbus register 0x00 and the pwm frequency is tuned to be 200hz with an appropriate capacitor at the fpwm pin. on the other hand, pwmi is fed with a 1khz 30% high pwm signal. when pwm_sel = 0 and pwm_md = 0, the device is in dpst operation where dpst brightness = 15% pwm dimming at 200hz. ? all reserved bits return a ?0? when read. ? all reserved bits have no functional effect when written. ? all defined control bits return their current, latched value when read. ? a value of 1 written to bl_ctl turns on the bl in 4ms or less after the write cycle completes. the bl is deemed to be on table 3. operating modes selected by device control register bits 1 and 2 pwm_md pwm_sel mode x 1 pwmi mode 1 0 smbus mode 0 0 smbus and pwmi mode with dpst figure 23. descriptions of brightness control register register 0x00 pwm brightness control register brt7brt6brt5brt4brt3brt2brt1brt0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brt[7..0] = 256 steps of pwm brightness levels figure 24. descriptions of device control register register 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions pwm_md = pwm mode select bit (1 = absolute brightness, 0 = % change) default = 0 pwm_sel = brightness control select bit (1 = control by pwmi, 0 = control by smbus) default = 0 bl_ctl = bl on/off (1 = on, 0 = off) default = 0 dpst brightness cbt pwmi = (eq. 15) isl97635a
21 fn6564.2 december 22, 2008 when bit 3 bl_stat of register 0x02 is 1 and register 0x09 is not 0. see figures 23 and 24. ? a value of 0 written to bl_ctl immediately turns off the bl. the bl is deemed to be off when bit 3 bl_stat of register 0x02 is 0 and register 0x09 is 0. see figures 23 and 24. ? ** note that the behavior of register 0x00 (brightness control register) is affected by certain combinations of the control bits, as shown in table 3 ?operating modes selected by device control register bits 1 and 2.? ? when an smbus mode is selected, register 0x00 reflects the last value written to it. but, when any non-smbus mode is selected, register 0x00 reflects the current brightness value based on the current mode of operation, with the exception of smbus mode with dpst, where pwm_md = 0 and pwm_sel = 0. ? when smbus mode with dpst is selected, register 0x00 reflects the last value wr itten to it from smbus. ? when a write to register 0x01 (device control register) causes the backlight controller to transition to an smbus mode, the brightness of the bl does not change. on the other hand, when a write to register 0x01causes the backlight controller to transition to a non-smbus mode, the brightness of the bl chang es as appropriate for the new mode. ? the default value for register 0x01 is 0x00. fault/status register (0x02) this register has six status bits that allow monitoring of the backlight controller?s operating stat e. bit 0 is a logical ?or? of all fault codes to simplify error detection. not all of the bits in this register are fault related (bit 3 is a simple bl status indicator). the remaining bits are reserved and return a ?0? when read and ignore the bit value when written. all of the bits in this register are read-only, with the excepti on of bit 0, which can be cleared by writing to it. ? a read byte cycle to register 0x02 indicate s the current bl on/off status in bl_stat (1 if the bl is on, 0 if the bl is off). ? a read byte cycles to register 0x2 also returns fault as the logical or of thrm_shdn, ov_curr, 2_ch_sd, and 1_ch_sd should these events occur. ? 1_ch_sd returns a 1 if one or more channels have faulted out. ? 2_ch_sd returns a 1 if two or more channels have faulted out. ? a fault will not be reported in the event the bl is commanded on and immediat ely off by the system. ? when fault is set to 1, it will remain at 1 even if the signal which sets it goes away. fault will be cleared when the bl_ctl bit of the device control register is toggled or when written low. at that time, if the fault condition is still present or reoccurs, fault will be set to 1 again. bl_stat will not cause fault to be set . ? the controller will not indicate a fault if the vbl+ goes away, whether or not the leds were on at the time of the power loss. this can occur if there is some hang condition that causes the user to force the system off by holding the power button down for 4s. default value for register 0x02 is 0x00. identification register (0x03) the id register contains thr ee bit fields to denote the led driver (always set to 1), manuf acturer and the silicon revision of the controller ic. the bit fiel d widths allow up to 16 vendors with up to eight silicon revision s each. in order to keep the number of silicon revisions low, the revision field will not be updated unless the part will make it out to the user?s factory. thus, if during the engineer ing development process three silicon spins were needed, the next available revision id would be used for all three spins until that same id made it to the factory. except bit 7 which has to be 1, all of the bits in this register are read-only. ? vendor id 9 represents intersil corp. ? default value for register 0x03 is 0xc8. the initial value of rev shall be 0. subsequent values of rev will increment by 1. isl97635a
22 fn6564.2 december 22, 2008 register 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit bit assignment bit field definitions bit 5 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) bit 4 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bit 3 bl_stat = bl status (1 = bl on, 0 = bl off) bit 2 ov_curr = input overcurrent (1 = overcurrent condition, 0 = current ok) bit 1 thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) bit 0 fault = fault occurred (logic ?or? of all of the fault conditions) figure 25. descriptions of fault/status register register 0x03 id register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 bit 7 = 1 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit assignment bit field definitions mfg[3..0] = manufacturer id. see ?identification register (0x03)? on page 21. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents intersil id data 10 to 14 in decimal are reserved data 15 in decimal manufacturer id is not implemented rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) figure 26. descriptions of id register isl97635a
23 fn6564.2 december 22, 2008 dc brightness control register (0x07) the dc brightness control regi ster 0x07 allows users to have additional dimming flexibility as: 1. achieving effectively 16-b it of dimming control when combined dc dimming with pwm dimming or 2. achieving visual or audio noise free 8-bit dc dimming over potentially noisy pwm dimming. the bit assignment is shown in figure 27. all of the bits in this register can be read or write. steps 0 to 255 represent the linear steps of current adjustment in dc on the fly. it can also be considered as the peak current factory calibration feature to account for various led production batches variations but external eeprom settings storing and restoring are required. ? an smbus write byte cycle to register 0x07 sets the brightness level in dc only. ? an smbus read byte cycle to register 0x07 returns the current dc brightness level. ? default value for register 0x07 is 0xff. configuration register (0x08) the configuration register allows users to set 2 levels of channel short-circuit thresholds or disable it. it also allows users to set the boost conversion switching frequency between 1.2mhz and 600khz. the bit assignment is shown in figure 28. default value for register 0x08 is 0xff output channel mask/fault readout register (0x09) this register can be read or write; the bit position corresponds to the channel. for example, bit 0 corresponds to ch0 and bit 5 corresponds to ch5 and so on. when writing data to this register , it enables the channels of interest. when reading data from this register, any disabled channel and any faulted out channel will read as 0. this allows the user to determine which channel is faulty and optionally not enabling it to allow the rest of the system to continue to function. additionally, a faulted out channel can be disabled and re-enabled in order to allow a retry for any faulty channel without havi ng to power-down the other channels. the bit assignment is shown in figure 29. default for register 0x09 is 0xff. figure 27. descriptions of dc brightness control register register 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) b it 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brtdc[7..0] = 256 steps of dc brightness levels register 0x08 configuration register reserved reserved reserved reserved reserved fsw vsc1 vsc0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions vsc[1..0] 2 levels of short-circuit thresholds (1 = 8v, 0 = 3.1v, accuracy 15%) fsw[2] 2 levels of switching frequencies (1 = 1,200khz, 0 = 600khz) figure 28. descriptions of configuration register isl97635a
24 fn6564.2 december 22, 2008 components selections according to the inductor voltage-second balance principle, the change of inductor current during the switching regulator on-time is equal to the change of inductor current during the switching regulator off-time. since the voltage across an inductor is: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the s witching period. v d is schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle resp ectively as equations 18 and 19: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, improving system stability. the high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. in boost mode, input current flows continuously into the inductor, with an ac ripple component proportional to the rate of inductor charging only and smaller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. inductor the selection of the inductor should be based on its maximum current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. its maximum current capability must be adequate to handle the peak current at the worst ca se condition. if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be derived from the fact that the voltage across the inductor during the off-period can be shown as equation 20: the choice of 85% is just an average term for the efficiency approximation. the first term is average current that is inversely proportional to the input voltage. the second term is inductor current change that is inversely proportional to l and f s . as a result, for a given switching frequency and minimum input voltage the system operates, the inductor i sat must be chosen carefully. at a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. thus, the higher the inductance, the lower the peak current capability. the isl97635a current limit may also have to be taken into account. output capacitors the output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. output ripple voltage consists of the discharge of the output capacitor for i lpeak during fet on figure 29. output channel register register 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions ch[5..0] ch5 = channel 5, ch4 = channel 4 and so on v l l i l t ? = (eq. 16) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 17) v o v i 11d ? () ? = ? (eq. 18) dv o ( v i ) v o ? ? = (eq. 19) il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f s ) ? ? [] ? + ? = (eq. 20) isl97635a
25 fn6564.2 december 22, 2008 and the voltage drop due to flowing through the esr of the output capacitor. the ripple voltage can be shown as equation 21: the conservation of charge principle in equation 19 also brings up a fact that during the boost switch off-period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. as a result, the users need to select an output capacitor with low esd and with a enough input ripple current capability. output ripple v co can be reduced by increasing c o or f s , or using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small to medium sized lcd backlight applications due to their cost, form factor, and low esr. a larger output capacitor will also ease the driver respond during pwm dimming off-period due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the next on-period that minimizes transient current. the output capacitor is also needed for compensation and in general 2x4.7f/50v ceramic capacitors are suitable for the notebook display backlight applications. schottky diode a high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse leakage current will minimize losses, making schottky diodes the preferred choice. although the schottky diode turns on only during the boost switch off-period, it carries the same peak current as the inductor?s, and therefore, a suitable current rated schottky diode must be used. applications high current applications each channel of the isl97635a can support up to 35ma. for applications that need higher current, multiple channels can be grouped to achieve the desirable current. for example, the cathod e of the last led can be connected to iin0 to iin2; this configur ation can be treated as a single string with 105ma current driving capability. . multiple drivers operation for large lcd panels where more than 6 channels of leds are needed, multiple isl97635as with each driver having its own supporting components can be controlled together with the common smbus. while the isl97635a does not have extra pins strappable slave ad dress feature, a separate en signal can be applied to each driver for asynchronous operation. a trade-off of such scheme is that an exact faulty channel cannot be identified if the en/pwmi signal is common to all drivers. 16-bit dimming the smbus controlled pwm and dc dimmings can be combined to effectively provide 16 bits of dimming capability, which can be valuable for automotive and avionics display applications. figure 32 illustrates one programming example where 256 steps of pwm dimming can be programmed between each dc dimming steps or vice versa. v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 21) figure 30. grouping multiple channels for high current applications iin0 iin1 iin2 v out figure 31. multiple drivers operation smbclk smbdat en/pwmi smbclk smbdat en/pwmi smbclk smbdat en1 en2 isl97635a
26 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6564.2 december 22, 2008 rgb led backlight or scrolling backlight operation the smbus control features of pwm dimming, dc dimming, and random channels selection have offered many driving possibilities. for example, red, green, and blue leds can be arranged in ch0 and ch1, ch2 and ch3, ch4 and ch5 respectively such that each group can be controlled independently in sequential order for rgb led backlighting applications. compensation the isl97635a has two main elements in the system; the current mode boost regulator and the op amp based multi-channel current sources. the isl97635a incorporates a transconductance amplifier in its feedback path to allow the user some levels of adjustment on the transient response and better regulation. the isl97635a uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation. the slow voltage loop must be compensated for stable operation. the compensation network is a series rc, cc1 network from comp pin to ground and an optional cc2 capacitor connected to the comp pin. the rc sets the high frequency integrator gain for fast transient response and the cc1 sets the integrator zero to ensure loop stability. for most applications, rc is in the range of 200 to 3k and cc1 is in the range of 27nf to 37nf. depending upon the pcb layout, a cc2, in range of 100nf, may be needed to create a pole to cancel the output capacitor esr?s zero effect for stability. the isl97635a evaluation board is configured with rc1 of 500 , cc1 of 33nf, and cc2 of 0, which achieves stability. in the actual applications, these values may need to be tuned empirically but the recommended values are usually a good starting point. figure 32. 16-bit dimming illustration step 255 pwm control step 0~255 dc control step 254 pwm control step 1 pwm control steps 0~255 dc step 0 pwm control isl97635a
27 fn6564.2 december 22, 2008 vin pwmi/en r5 10k c6 4.7/50v c11 1/10v r6 10k r4 39k d1 ss15 ovp r3 1m smbclk 1 smbdat 2 fpwm 3 pwmo 4 gnd 5 nc 7 nc 8 iin5 9 iin4 10 rset 11 iin1 14 iin0 15 ovp 16 pgnd 17 pgnd 18 lx 20 fault 21 comp 22 vin 23 vdc 24 pwmi/en 6 iin3 12 lx 19 iin2 13 u1 isl97635a c1 10/25v c10 33n r7 500 c13 27n/6.3v c14 220n/6.3v c7 4.7/50v jp26 c12 0.1/10v c2 0.1/25v c4 10/25v 1 2 5 6 4 3 q1 fdma530pz gnd vlogic smbdat smbclk led1 led2 led3 led4 led5 led6 led7 led8 led9 led10 led11 led12 led13 led14 led15 led16 led17 led18 led19 led20 led21 led22 led23 led24 led25 led26 led27 led28 led29 led30 led31 led32 led33 led34 led35 led36 led37 led38 led39 led40 led41 led42 led43 led44 led45 led46 led47 led48 led49 led50 led51 led52 led53 led54 l1 8.2h l1 : ihlp-2525bd-01 vishay inductor, d1 : ss15 - vishay schottky diode, 5 notes: figure 33. typical application circuit c20 for 2 layers board, layout pgnd (noisy ground) on top layer and agnd (quiet ground) on bottom layer. tie pgnd and agnd only at one point by doing this: bridge u1 pgnd (pins 18 and 19) and agnd (pin 5) to the package thermal pad. put multiple vias on the thermal pad that connects to the bottom side agnd. r2 36.6k isl97635a
28 fn6564.2 december 22, 2008 isl97635a package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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